With the rapid development of integrated circuit technologies, there has been a continuous drive to reduce the size of these circuits. As the devices are miniaturized and features become more closely spaced, the tolerance of process parameters becomes more critical because minute defects will cause the devices to fail. For example, layers of conductive and insulative materials are generally patterned to form a desired structure and to perform certain functions, such as transistors, resistors and metal lines.
The planarization of these layers greatly influences the efficacy of the subsequent photolithography. If the topography is not smooth enough, the patterned layer would be distorted after the patterning. In addition, the uneven surface of these layers will cause problems in subsequent overlying layers.
Prior arts have been developed to planarize the surface of a layer. For example, an organic-based glass such as spin on glass (SOG) is typically used for planarization. In general, the SOG layer is formed over a layer by using a spin-coating method. However, the spin-coating method is primarily effective for localized planarization. In addition, an etching back is generally used after the SOG is coated. To achieve an equal etching rate of both the underlying oxide layer and SOG layer is difficult and depends upon the features of in the underlying layers.
Another popular method of planarization is the use of borophosphosilicate glass (BPSG). Generally, BPSG requires a deposition step and an etch step to achieve a planar surface. However, where there is a great step height between the cell and cell boundary (or periphery area), the topography after the formation of the BPSG is uneven. In addition, the process requires a thermal step to reflow the BPSG at high temperature. Therefore, what is required is a method to solve the aforesaid deficiencies.